First-in first-out (FIFO) buffers, a form of shared memory, are often used at the ingress of input/output (I/O) interfaces of data packet communications systems to temporarily store data packets before they are transmitted from the I/O interface. However two problems can occur in such instances. The first problem occurs when the ingress data rate to the FIFO buffer, also referred to herein as the ingress FIFO data rate, is slower than the egress I/O interface data rate, also referred to herein as the egress I/O data rate. Since the ingress FIFO data rate is slower than the egress I/O data rate, pauses in transmission will occur if transmission of a data packet from the FIFO buffer is started before the entire data packet is received by the I/O interface. These pauses result in corruption of the transmitted data packet, their cause being referred to as under-run conditions. The second problem is that FIFO buffers are required for each I/O interface port, which can make data packet communications systems with a large number of I/O interface ports difficult and costly to build. This is because of the large amount of memory required to implement the FIFO buffers for a large number of I/O interface ports. Furthermore, if each FIFO buffer requires a large amount of memory, integrating the FIFO buffers into a field programmable gate array (FPGA) device, typically used in data packet communications systems, becomes costly and difficult due to the limited amounts of internal memory in such devices.
A known way to avoid the aforementioned problems is to ensure that ingress FIFO data rates are always greater than the egress I/O interface rates. However, this solution can impose a requirement for higher speed interfaces upstream, such as across a midplane or backplane of the data packet communication system, thereby increasing complexity, cost, power consumption, and reducing system reliability.
Another known way to avoid the aforementioned problems is to employ FIFO buffers that store entire packets prior to transmission in an effort to eliminate under-run conditions and packet corruption. However, these FIFO buffers require enough memory to store entire packets which at times could be quite large. The unfortunate result of this large memory requirement is that it puts practical limits on the number of I/O interface ports that can be supported, or it can make integrating a design into an FPGA device difficult unless external memory devices are used, which increases manufacturing costs of the data packet communications system.
Accordingly, there is a need for a technique of buffering data packets at the ingress of an I/O interface that does not require a large amount of memory per I/O interface port and that can reduce the occurrence of under-run errors.